1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same and more particularly to a semiconductor device intended to reduce and stabilize the wiring contact resistance and a method for manufacturing the same.
2. Description of the Related Art
Large scale integrations (LSIs) known as representing semiconductor devices are roughly classified into memory devices and logic devices, the former of which are particularly remarkable in development with recent improvements in semiconductor manufacturing technologies. The memory devices may be further classified into Dynamic Random Access Memories (RAMs) and Static Random Access Memories (SRAMs), both of which are in large part comprised of Metal Oxide Semiconductor (MOS) transistors, which are excellent in integration density. Also, a DRAM may enjoy the above-mentioned merits in terms of integration density as compared to an SRAM, to reduce the manufacturing cost, thus finding wider applications in various storage systems including information-related ones.
A DRAM as a semiconductor device uses a capacitor as the information-storing capacitive element in a manner that presence of charge in the capacitor determines information stored, so that as the device is reduced in size due to improved fine patterning technologies, the area occupied by each capacitor formed in a semiconductor substrate is restricted. To solve this problem, it is necessary to increase the capacitance of each capacitor. If that capacitance is not enough to store information, the relevant device is liable to malfunction due to external noise signal etc., thus giving rise to an error represented by a soft error.
As a structure of the capacitor intended to increase its capacitance by the above-mentioned restricted area of its own, an inner wall-type cylindrical structure is known. FIG. 8 is a cross-sectional view showing a conventional semiconductor device (first conventional embodiment) having such an inner wall-type cylindrical structure. The semiconductor device, as shown in the figure, has such a configuration that an n-type diffusion region 53, surrounded by a device-isolating insulator film 52 consisting of a field oxide film, is formed therein which selectively has a source or drain region in an active region of for example a p-type silicon substrate 51, so that between the regions 53 is provided via a gate oxide film 54 a gate electrode 55 , which is in turn covered with a first inter-layer insulator film 56. Moreover, a second inter-layer insulator film 57 is formed in such a manner as to cover the whole surface, in which a bit contact 58 is buried to be connected to one diffusion region 53 with the other diffusion region 53 being connected with a conducting plug 60 buried in a contact hole 59 formed in the first insulator film 57.
A third inter-layer insulator film 61 is formed covering the whole surface, in which is formed a contact hole 62 to expose the conducting plug 60, to which is connected an inner wall-type cylindrical capacitor 65. This capacitor 65 consists of a lower electrode (storage electrode) 66 provided at the inner wall and the bottom of the contact hole 62 to be connected to the conducting plug 60, a capacitive insulator film 67 provided to cover this lower electrode 66 and the third inter-layer insulator film 61, and an upper electrode 68 provided to cover this capacitive insulator film 67.
Here, the conducting plug 60, the lower electrode 66, and the upper electrode 68 consist of for example a polycrystalline silicon film. The capacitive insulator film on the other hand consists of a known insulator film such as oxide-nitride-oxide (ONO) film or oxide-nitride (ON) film.
A fourth later-layer insulator film 71 is formed to cover the whole surface, in which is formed a contact hole 72 to expose the upper electrode 68 of the capacitor 65, to which upper electrode 68 is connected via a barrier metal film 73 an upper wiring (contact) 76 consisting of a conducting plug 78 and an aluminum film. This upper electrode 76 is connected to a peripheral circuit. The upper wiring 76 is covered with a reflection-preventing film 77 consisting of a titanium nitride (TiN) film. This reflection-preventing film 77 acts to prevent irregular reflection of a light produced when an aluminum film is patterned to form the upper wiring 76.
The barrier metal layer 73 consists of a titanium film 74 as the lower film and a titanium nitride film 75 as the upper film, thus acting to prevent aluminum constituting the upper wiring 76 from breaking through the diffusion region 53 up to the silicon substrate 51 caused by heat treatment at the time of hydrogen alloying when a contact hole is formed in the diffusion region 53.
The titanium film 74 constituting the lower film of the barrier metal film 73 is formed to suppress stable the contact resistance with a diffusion region (especially p-type diffusion region) when a contact is formed in the diffusion region 53.
In the manufacturing of the above-mentioned semiconductor device, when connecting a contact through the barrier metal film 73 up to the upper electrode 68, the contact hole 72 is formed in the fourth inter-layer insulator film 71 beforehand to form the barrier metal film 73 thereon, in such a manner that the contact hole 72 and the barrier metal film 73 are formed at the same time as other regions which need to be connected electrically. When, for example, the diffusion region 53 in the silicon substrate 51 or the gate electrode 55 thereon needs an electrical connection, a contact hole and a barrier metal film are formed simultaneously to provide an electrical connection to these regions.
However, since in such a case the above-mentioned contact hole 72 is formed relatively shallow as compared to a contact hole to be formed in a thick inter-layer insulator film on the diffusion region 53 or the gate electrode 55, when a barrier metal film is formed at the same time as each of these contact holes, the barrier metal film is formed thickest on the contact hole 72 formed in the thinnest upper electrode 68. When a barrier metal film is formed thinner on the contact hole 72, on the other hand, a barrier metal film formed on the contact hole formed in the deepest diffusion region 53 becomes thinner, which provides a very thin titanium film, which in turn reduces an effect of suppressing the above-mentioned contact resistance low and stable, thus leading to a problem of an increase in the contact resistance of a contact formed in the contact hole. To eliminate this problem, therefore, it is unavoidable to form the barrier metal film 73 relatively thick on the upper electrode 68 of the capacitor 65.
Thus formed barrier metal film 73 undergoes a subsequent heat treatment (annealing) process, during which its component titanium and the underlying upper electrode 68-component polycrystalline silicon film react with each other (silicide reaction), to form titanium silicide. Thus formed titanium silicide acts to give a lower and stable resistance.
FIG. 10 is a cross-sectional view showing a conventional semiconductor device (second conventional embodiment) provided with an inner wall-type cylindrical structured capacitor according to another embodiment. As shown in the figure, in this semiconductor device, a conductive film (break-through preventing film) 79 consisting of a polycrystalline silicon film formed with the gate electrode 55 simultaneously is provided at the first inter-layer insulator film 56 to form the capacitor 65 and subsequently a contact hole 80 which breaks through the upper electrode 68 up to the conductive film 79, in order to form the barrier metal layer 73 on this contact hole 80. The upper electrode 68 of the capacitor 65 is connected with the metal film 73 at part of the side of the batter metal film 73.
Since, in the above-mentioned first conventional semiconductor device, at the contact formed at the upper electrode of the capacitor, the barrier metal-component titanium has a large thickness as compared to the capacitor""s upper electrode-component polycrystalline silicon, supply of polycrystalline silicon is liable to go insufficient at the time of silicide reaction to have voids at part of the upper electrode, which leads to a problem of an increase in and instability of the resistance of the contact of a wiring up to the upper electrode through the barrier metal film.
That is, since, as mentioned above, the upper electrode 68 of the capacitor 65 has the barrier metal film formed relatively thick thereon, as shown in FIG. 9A, supply of titanium, which promotes the silicide reaction, is large and, at the same time, the polycrystalline silicon film is thin, so that supply of polycrystalline silicon becomes insufficient at the time of the silicide reaction. When, moreover, the component in the thickness direction of the polycrystalline silicon film is completely eliminated, the silicide reaction proceeds in a lateral direction (arrow direction) of the polycrystalline silicon film as shown in FIG. 9B. If, in this case, supply of polycrystalline silicon cannot catch up with the silicide reaction, part of the polycrystalline silicon film has a void 81. In the worst case, the wiring suffers from poor continuity.
The occurrence of the void in this case is considered to depend on a proportion in area between (titanium silicide/silicon interface) and titanium, so that the void is liable to occur when a relationship of ((area of titanium) greater than  greater than (area of (titanium silicide/silicon interface)) is established. Therefore, the void occurs in an easier manner as the barrier metal film 73 component titanium increases in thickness.
Since in the above-mentioned second conventional semiconductor device, on the other hand, in contrast to the above-mentioned first conventional embodiment, the relationship of ((area of titanium) greater than  greater than (area of (titanium silicide/silicon interface)) is not established, the void can be prevented from occurring; however, the conductive film 79 is provided deep in the inter-layer insulator film, thus problematically acting as a restrictive obstruction in layout.
That is, since, in the above-mentioned second conventional embodiment, the presence of the conductive film 79 makes it impossible to form a wiring etc. passing through the relevant region, such a layout-wise restriction cannot be disregarded in a fine-patterned structure. Since also, in this second conventional embodiment, the barrier metal film 73 is connected at its side with the upper electrode 68, it is impossible to form a side-wall insulator film intended to prevent a short circuit between mutually adjacent wirings in a fine-patterned structure, which constitutes another problem.
In view of the above, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same intended to reduce and stabilize the contact resistance by suppressing void occurrence, likely at the time of the silicide reaction, at a polycrystalline silicon wiring.
According to a first aspect of the present, there is provided a semiconductor device having such a configuration that in a second insulator film which covers a first polycrystalline silicon film provided in a first insulator film which covers a semiconductor substrate, a first contact hole is formed to expose part of said polycrystalline silicon film, and through said first contact hole, a wiring is connected, via a barrier metal film composed of an underlying titanium film, to said polycrystalline silicon film, wherein
a trench which has a width larger than a width of said first contact hole is formed in said first insulator film below said first contact hole and a second polycrystalline silicon film is provided in said trench.
Also, according to a second aspect of the present invention, there is provided a semiconductor device having such a configuration that in a second insulator film which covers a first polycrystalline silicon film provided on a first insulator film which covers a semiconductor substrate, a first contact hole is formed to expose part of said polycrystalline silicon film, a second contact hole having a depth different from a depth of said first contact hole is formed in an insulator film including said first insulator film and said second insulator film in a diffusion region of said semiconductor substrate, and through said first contact hole, a wiring is connected via a barrier metal film composed of an underlying titanium film to said polycrystalline silicon film, wherein a trench which has a width larger than a width of said first contact hole is provided in said insulator film below said first contact hole and a second polycrystalline silicon film is provided in said trench.
In the foregoing first/second aspect, a preferable mode is one wherein a film thickness of a polycrystalline silicon region formed in said trench by said second polycrystalline silicon film is set corresponding to a film thickness of said underlying titanium film of said barrier metal film at a bottom of said first contact hole.
Also, a preferable mode is one wherein said second polycrystalline silicon film is so provided in said trench as to be fully buried therein.
Also, a preferable mode is one wherein said second polycrystalline silicon film is not fully buried in said trench and said first contact hole is so provided as to approximately reach a bottom of said trench.
Furthermore, a preferable mode is one wherein a side-wall insulator film is provided on a side wall of said first contact hole and a side wall of said second contact hole.
According to a third aspect of the present, there is provided a semiconductor device having such a configuration that a capacitor is formed so as to be electrically connected to one diffusion region in a semiconductor substrate and includes a lower electrode provided in a second contact hole formed in a first insulator film on said semiconductor substrate, a capacitive insulator film provided on said lower electrode and said first insulator film, and a polycrystalline silicon-made upper electrode provided on said capacitive insulator film, a first contact hole is formed in a second insulator film which covers said upper electrode, to expose part of said upper electrode, and through said first contact hole, a wiring is connected via a barrier metal film composed of an underlying titanium film to said upper electrode, wherein
a trench which has a width larger than a width of said first contact hole is provided in said first insulator film below said first contact hole and a polycrystalline silicon film which constitutes a dummy capacitor is provided in said trench.
In the foregoing third aspect, a preferable mode is one wherein a third contact hole which differs from said first contact hole in depth is formed in an insulator film which includes said first insulator film and said second insulator film and which covers said semiconductor substrate, in a diffusion region of said semiconductor substrate.
Also, a preferable mode is one wherein a film thickness of a polycrystalline silicon region formed in said trench by said polycrystalline silicon film is set corresponding to a film thickness of said underlying titanium film of said barrier metal film at a bottom of said first contact hole.
Also, a preferable mode is one wherein said poly-crystalline silicon film is so provided as to be fully buried in said trench.
Also, a preferable mode is one wherein said polycrystalline silicon film is not fully buried in said trench and said first contact hole is so provided as to approximately reach a bottom of said trench.
Also, a preferable mode is one wherein a side-wall insulator film is provided on a side wall of said first contact hole and said second contact hole.
According to a fourth aspect, there is provided a method of manufacturing a semiconductor device, including the steps of:
forming a diffusion region in a semiconductor substrate and then connecting a conducting plug to said diffusion region, to form a memory-cell selecting transistor;
forming a first insulator film so as to cover said conducting plug and then forming a second contact hole in said first insulator film so as to expose said conducting plug and, at the same time, forming a trench so as not to expose said plug;
forming a conductive film in said second contact hole and said trench simultaneously, to constitute a lower electrode of a capacitor and a lower electrode of a dummy capacitor;
forming capacitive insulator film so as to cover both of said electrodes and then forming an upper electrode made of polycrystalline silicon on said capacitive insulator film to form a capacitor and a dummy capacitor;
forming a second insulator film so as to cover said upper electrode of said capacitor and then forming a first contact hole smaller in width than a second trench covered with said capacitive insulator film formed in said trench, in said second insulator film so as to expose said upper electrode of said dummy capacitor and, at the same time, forming a third contact hole which differs in depth from said first contact hole, in an insulator film which includes said first insulator film and said second insulator film;
forming a barrier metal film which has an underlying film made of titanium, in such a way that a titanium film which has a film thickness corresponding to a film thickness of a polycrystalline silicon region formed in said trench by polycrystalline silicon of said upper electrode is formed at a bottom of said first contact hole; and
conducting heat treatment of reacting titanium of said underlying film of said barrier metal film and polycrystalline silicon of said upper electrode.
A preferable mode is one wherein in said capacitor forming step, said upper electrode is formed in such a way that polycrystalline silicon of said upper electrode is fully buried in said trench.
Also, a preferable mode is one wherein in said capacitor-forming step, said upper electrode is formed in such a way that polycrystalline silicon is not fully buried in said trench and, at the same time, said first contact hole is so formed as to reach a bottom of said trench.
Also, a preferable mode is one that wherein further including a step of forming a side-wall insulator film on said first side wall and said third wall after said contact hole-forming step.
With the above configurations, a contact hole is formed in an insulator film which covers a polycrystalline silicon film, to expose part of this polycrystalline silicon film, in an insulator film below which contact hole is formed a trench larger than the contact hole in width, in which trench is provided a polycrystalline silicon film, so that there is no insufficiency in supply of polycrystalline silicon at the time of the silicide reaction between polycrystalline silicon and titanium of the barrier metal film.
Also, a contact hole is formed in an insulator film which covers a polycrystalline silicon film, to expose part of this polycrystalline silicon film, in an insulator film below which contact hole is formed a trench larger than the contact hole in width, in which trench is provided a polycrystalline silicon film, so that even if the contact hole is over-etched, the polycrystalline silicon film on the insulator film is not separated from the polycrystalline silicon film in the trench, thus giving rise to no problem in an electrical connection between a wiring and the polycrystalline silicon film when a side-wall film is formed on the side walls of the contact hole.
Therefore, the present invention can suppress the occurrence of voids which is likely at a polycrystalline silicon wiring at the time of the silicide reaction, thus reducing and stabilizing the contact resistance.